The present invention relates generally to semiconductor manufacturing processes, and, more particularly, to a method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial material.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. This includes the width and spacing of conductive features and the surface geometry, such as corners and edges of various features. Since numerous conductive features are typically present on a semiconductor wafer, the trend toward higher device densities is a notable concern.
The requirement of small features (and close spacing between adjacent features) in turn requires high-resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. More specifically, it is a technique used for integrated circuit fabrication in which a silicon slice (i.e., the wafer) is coated uniformly with a radiation-sensitive film (i.e., the resist), and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template (i.e., the photomask) for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photomask causes a chemical transformation in the exposed areas of the coating, thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. However, such lithography is not without limitations. Patterning features having dimensions of about 0.10 μm or less with acceptable resolution is difficult at best, and almost impossible in certain circumstances. At these dimensions, the tolerances become very difficult to control. Patterning conductive features, including conductive lines and conductive silicon substances (such as amorphous silicon and polysilicon), with small dimensions is required in order to participate in the continuing trend toward higher device densities.
As chip dimensions are scaled to 90 nanometers and below, it is becoming increasingly difficult to scale the device tolerances around those dimensions. For example, at the 90 nm technology, existing best case through-pitch behavior for a 55 nm gate conductor is about 10 nm. However, this 10 nm value does not include other sources of across-chip linewidth variation (ACLV) such as mask variation, optical aberrations and focus variation. For the 65 nm mode, there currently exists 40 nm of through-pitch critical dimension (CD) variation for the gate conductor (without optical proximity correction), using alternate phase shifting masks (PSM).
Accordingly, it has become desirable to obtain alternative methods of scaling the gate conductor that provide enhanced resolution, tolerance control, and improved critical dimension values.